低电压Σ-Δ调制器关键技术及设计实例  

Key Issues for Low Voltage Σ-Δ Modulator and Design Example

作　　者：刘爱荣[1] 孔耀辉[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微电子学》2008年第5期727-730,共4页Microelectronics

摘　　要：介绍了低电压开关电容Σ-Δ调制器的实现难点及解决方案,并设计了一种1V工作电压的Σ-Δ调制器。在0.18μm CMOS工艺下,该Σ-Δ调制器采样频率为6.25MHz,过采样比为156,信号带宽为20kHz;在输入信号为5.149kHz时,仿真得到Σ-Δ调制器的峰值信号噪声失真比达到102dB,功耗约为5mW。Difficulties in implementing low voltage switched-capacitor ∑-△ modulator were discussed, and solutions were presented. As an example, a 1 V ∑-△ modulator was designed. The circuit was simulated based on 0. 18 μm CMOS process. And simulation results showed that, for a sampling rate of 6.25 MHz and an oversampling ratio of 156, the modulator achieved an SNDR of 102 dB, with a power dissipation of about 5 mW.

关 键 词：∑-△调制器 开关电容 CMOS电路 

分 类 号：TN761[电子电信—电路与系统]