SOC用400～800MHz锁相环IP的设计  

Design of 400-800 MHz PLL IP for SOC

作　　者：樊勃[1] 戴宇杰[1] 张小兴[1] 吕英杰[1] 

机构地区：[1]南开大学微电子研究所,天津300071

出　　处：《微电子学》2008年第5期743-747,共5页Microelectronics

基　　金：天津市科技发展计划科技攻关项目资助(043182111)

摘　　要：设计了一个基于锁相环结构、可应用于SOC设计的时钟产生模块。电路输出频率在400～800MHz,使用SMIC0.18μm CMOS工艺进行流片。芯片核心模块工作电压为1.8V和3.3V。根据Hajimi关于VCO中抖动(jitter)的论述,为了降低输出抖动,采用一种全差动、满振幅结构的振荡器;同时,通过选取合适的偏置电流,实现对环路带宽的温度补偿。流片后测试结果为:输出频率范围400～800MHz,输入频率40～200MHz;在输出频率为800MHz时,功耗小于23mA,周期抖动峰峰值为62.5ps,均方根(rms)值为13.1ps,芯片面积0.6mm2。A clock generator for SOC based on phase-locked loop （PLL）was presented. The prototype chip was fabricated in SMIC＇s 0.18 μm CMOS technology. Based on the analysis of Hajimi about jitter in VCO, a fully differential architecture of VCO with full swing oscillation was proposed. A proper bias current was chosen to compensate the loop bandwidth variation over temperature. Test results showed that the clock generator had an input frequency range from 400 MHz to 800 MHz, and a period jitter of 62. 6 ps （pk-pk）and 13.1 ps （rms）at 800 MHz. The whole clock generator occupies a chip area of 0. 6 mm^2 , and consumes less than 23 mA of power.

关 键 词：时钟产生电路 锁相环 压控振荡器 

分 类 号：TN402[电子电信—微电子学与固体电子学]