一种面向多核DSP的小容量紧耦合快速共享数据池  

A Small Close-Coupled Fast Shared Data Pool for Multi-Core DSPs

作　　者：陈书明[1] 汪东[1] 陈小文[1] 万江华[1] 

机构地区：[1]国防科技大学计算机学院微电子研究所,长沙410073

出　　处：《计算机学报》2008年第10期1737-1744,共8页Chinese Journal of Computers

基　　金：国家"八六三"高技术研究发展计划项目基金(2007AA01Z108);国家自然科学基金(60473079);教育部博士点基金(20059998026)资助~~

摘　　要：该文结合片上便笺式存储器(SPM)的结构特点,提出了一种面向异构多核DSP的新型小容量紧耦合共享存储结构——快速共享数据池(FSDP).FSDP在存储层次上与一级Cache平行,可以被访存指令直接访问,采用多体并行的结构、交叉访问模式和基于硬件信号灯的自动同步机制,支持多个DSP核的并行访问与快速的核间数据交换,两核之间交换单个数据只需4拍.该文构建了FSDP的模拟模型,并进行了RTL级设计实现和分析.多种典型测试程序的验证表明,FSDP对于DSP核间细粒度共享数据的传输具有很高的效率,相比同类的VS-SPM结构能够将程序性能提高37%,与传统的共享数据Cache结合使用能够将异构多核DSP的性能提高13%.Improving the performance of Multi-Core Digital Signal Processors （MC-DSPs） for embedded applications needs the support of higher memory bandwidth and more flexible memory structures. This paper proposes a new shared Scratch-Pad Memory （SPM） structure for MC- DSPs, Fast Shared Data Pool （FSDP）. FSDP is on the same hierarchy with L1 cache and can be directly accessed by LOAD/STORE instructions. FSDP is organized as parallel multi-bank structures with an interleaving access strategy and auto synchronous scheme based on hard signallamps. It supports high-speed parallel access and fast data words exchange. FSDP is a close-coupled share memory structure and it takes only four cycles to transmit a word between any two cores. The authors build the behavior simulator of FSDP and make its RTL implementation. The simulation with several typical benchmarks shows that FSDP is well suited to transmitting the fine-grain shared data in MC-DSPs. It achieves computation speedup ratio of 1.1 and 1.14 compared with traditional shared L2 caches and DMA units.

关 键 词：便笺存储器 共享存储 多核DSP 释放一致性 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]