AVS视频解码运动矢量预测模块的硬件设计  

Hardware Design for Motion Estimation of AVS

作　　者：王凌涛[1] 陈泳恩[1] 

机构地区：[1]同济大学中德学院通信软件及专用集成电路设计中心,上海200092

出　　处：《信息与电子工程》2008年第5期338-341,共4页information and electronic engineering

摘　　要：提出了一种适用于数字音视频编解码标准(AVS)的视频解码帧间运动矢量预测的解码方法,根据AVS宏块模式的特点,以统一的基本运算单元处理所有的解码模式,模块化流水计算,降低了硬件实现的复杂度。采用ASIC结构并使用Verilog语言进行设计、模拟,并成功通过了现场可编程门阵列验证。模块的每个功能块均为专用的VLSI结构,通过系统控制器控制各部分的运行,能有效地提高时钟频率,减小芯片的面积。使用0.18μmCMOS工艺库综合,在50MHz的时钟频率下工作时电路规模仅需1.6万门左右。Audio Video coding Standard（AVS） is the second generation audio and video coding standard of China. A decoding method for motion estimation of AVS is presented. According to the characteristic of AVS block, this architecture deals with all decoding modes with an uniform basic operation unit. The implementation difficulty is reduced as it operates in pipelining. This design and simulation is based on Verilog HDL. The whole design has been verified in Field Programmmable Gate Array（FPGA）. It is synthesized with 0.25 μ m CMOS cell library. The synthesized module is operated in 16 000 gates at 50 MHz.

关 键 词：数字音视频编解码标准 帧间预测 运动矢量解码 现场可编程门阵列 

分 类 号：TN919.81[电子电信—通信与信息系统]