基于FPGA的嵌入式多核处理器及SUSAN算法并行化  

Multi-Core Embedded Processor Based on FPGA and Parallelization of SUSAN Algorithm

作　　者：王洁[1] 张淑燕[1] 刘涛[1] 季振洲[1] 胡铭曾[1] 

机构地区：[1]哈尔滨工业大学计算机科学与技术学院,哈尔滨150001

出　　处：《计算机学报》2008年第11期1995-2004,共10页Chinese Journal of Computers

基　　金：山东省科技发展计划项目基金(2007GG10001020)资助

摘　　要：给出了四核心嵌入式并行处理器FPEP的结构设计并建立了FPGA验证平台.为了对多核处理器平台性能进行评测,提出了基于OpenMP的3种可行的图像处理领域的经典算法SUSAN算法的并行化方法:直接并行化SUSAN、图像分块处理和多图像并行处理,并对这3种并行算法在Intel四核心平台和FPEP的FPGA验证平台上进行性能测试.实验表明,3种并行算法在两种四核心平台下均可获得接近3.0的加速比,多图像并行处理在FPEP的FPGA验证平台可以获得接近4.0的加速比.Structure of 4-core embedded parallel processor is presented and FPGA validation platform that is called FPEP is built.To evaluate performance of multi-core processor platform,three feasible parallel algorithms with OpenMP on SUSAN that is a classic image processing algorithm： direct parallel SUSAN,image block processing and parallel processing of multiple images are proposed,and performance testing of these three parallel algorithms execute on Intel 4-core platform and FPGA validation platform of FPEP.Experimental results demonstrate that speedup ratio of three parallel algorithms on both 4-Core platforms is approximate 3.0,and speedup ratio of parallel processing of multiple images on FPGA validation platform of FPEP is approximate 4.0.

关 键 词：SUSAN FPGA OPENMP 多核处理器 图像处理 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]