一种基于FPGA的高速数据缓存的设计  

The Design of One Type of High-Speed Data Cache Based on FPGA

作　　者：夏金军[1] 庄奕琪[1] 包军林[1] 胡为[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《微计算机信息》2008年第32期226-228,共3页Control & Automation

摘　　要：本文设计了一种以FPGA为数据缓冲和逻辑控制单元的高速数据采集系统,提出了数据缓冲模块的两种不同实现方法,用以实现数据采集模块与数据处理模块之间的高速连接。通过软件仿真,详细分析了这两种方法的特性及其各自的适用场合。A high speed data acquisition system that use FPGA as the data cache and logic control unit was designed in this paper, and two different designing methods were put forward to realize the high speed data transmission between the data acquisition module and the disposal module. The properties and the proper applied situations of these two methods were analyzed through software in detail.

关 键 词：高速数据采集 现场可编程门阵列 先进先出 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]