DVB中高效BCH解码器的ASIC实现  

Design of An Efficient BCH Decoder in DVB and Its ASIC Implementation

作　　者：尧勇仕[1] 顾晓峰[1] 于宗光[1,2] 

机构地区：[1]江南大学信息工程学院,江苏无锡214122 [2]中国电子科技集团总公司第58研究所,江苏无锡214035

出　　处：《微计算机信息》2008年第32期292-293,296,共3页Control & Automation

摘　　要：介绍了数字电视广播(DVB)系统中BCH(762,752)解码器的设计及ASIC实现,提出了一种高效多功能的解码方法,并在XILINX公司的Virtex4器件上实现了验证。BCH解码器的系统级利用算法仿真对解码器作性能评估;采用VerilogHDL描述其硬件功能,对RTL级进行仿真、测试、一致性验证、综合和优化,解决了多时钟、亚稳态、毛刺以及测试覆盖率不全的问题。The design and ASIC implementation of a BCH （762, 752） decoder applied in the DVB system are presented. An efficient muhifunctional decoding method has been proposed and verified on XILINX Virtex4. The performance of the BCH decoder is evaluated by arithmetic simulation on the system level. The hardware function of the BCH decoder is described using VerilogHDL language, followed by the running of the RTL-level simulation, test, consistency verification, synthesis and optimization. Problems such as multiclock, metastable state, burr and incomplete testing coverage are solved.

关 键 词：数字电视广播(DVB) BCH解码器 专用集成电路 VerflogHDL 综合和优化 

分 类 号：TN919[电子电信—通信与信息系统]