基于排队论的多核处理器总线争用延时分析  

Analysis of Delay-time of Bus Contention on Multi-core Processor Based on Queuing Theory

作　　者：赵钊[1] 蒋烈辉[1] 赵秋霞[1] 刘辉[1] 刘振国[1] 

机构地区：[1]解放军信息工程大学信息工程学院,郑州450002

出　　处：《计算机工程》2008年第21期233-235,共3页Computer Engineering

摘　　要：多核处理器是处理器领域发展的必然趋势。多核之间的通信可以利用基于总线的共享cache实现,也可以通过片上互连技术实现。在采用共享总线的多核体系结构中,如何解决多个处理器核对总线控制权的竞争,以及对争用延时进行定量分析,是处理器体系结构优化的主要依据。为给体系结构优化提供量化依据,采用排队论方法建立总线争用延时量化分析模型,分析影响总线争用延时的各种相关因素。Multi-core is the trend in the field of processor. Communication in the multi-cores is realized either by the cache-share （cache memory）, which is based on the bus system, or by the interlink technology-on-chip. In the architecture of multi-core processor which is based on bus-share, how to solve the bus contention between the multi-cores, and quantificationally analyze the delay time is the main gist of architecture optimization. By introducing queuing theory, this paper quantificationally analyzes delay of bus contention, gains the factors which infect the delay of bus contention, and provides quantitative gist for architecture optimization.

关 键 词：多核处理器 排队论 量化分析 总线争用 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]