IA指令集仿真器的优化设计与实现  

Optimization Design and Realization of IA Instruction Set Simulator

作　　者：王颖[1] 王赛宇[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《无线电工程》2008年第11期49-51,共3页Radio Engineering

摘　　要：指令集仿真器是现代处理器设计和软件设计过程中不可缺少的一部分。指令集仿真器不仅有助于验证处理器和编译器的设计功能和性能,还能用来评估体系结构设计是否合理。现在指令集仿真器的广泛使用已经成为与此相关的软件设计的基础。为了得到高速的指令集仿真器,介绍了优化指令集仿真器的理论基础,在此基础之上提出了一系列优化方法,并采用ARM7处理器进行了逐一验证并取得了明显成效。Instruction Set Simulator （ISS） is an important part in modem processor and software design. ISS not only helps to validate the design of processor and compiler, but also evaluate the rationality of architecture design. Now, the extensive use of ISS already becomes the basis of software design related with that mentioned above. Aiming at obtaining high speed ISS, at first, this paper introduces the theory of optimizing ISS; secondly, it gives a series of optimizing technique; finally, it tests the performance of ISS model with the ARM7 processor one by one and acquires preferable result.

关 键 词：嵌入式 指令集仿真器 指令精确 优化 片上系统 译码 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]