H.264中1/4精度内插的硬件结构设计  

Architecture Design for Quarter-pixel Interpolation in H.264

作　　者：卜帆[1] 顾美康[1] 

机构地区：[1]上海师范大学数理信息学院,上海200234

出　　处：《电视技术》2008年第11期14-15,共2页Video Engineering

摘　　要：针对H.264中1/4精度像素内插的复杂算法,提出一种硬件实现结构。亮度分量中,对于4×4块的半像素计算,采用4个6抽头滤波器并行处理;同时整个计算过程,由一个状态机控制;对于1/4像素点计算,采用一个5×4的矩阵存储体完成对所有点的1/4精度计算。色度分量中,采用移位和加法替代乘法完成1/8精度内插。实验结果表明,此结构可完成对于高清以及CIF图像的实时解码计算,且占用逻辑资源少。In this paper,a hardware architecture for quarter-pixel interpolation in H.264 is proposed. As for the luminance component,four parallel 6 coefficients filters are used for half pixel calculating in 4×4 block; the state machine is used to control the whole process in the meantime; the 5×4 register array is used in order to compute quarter-pixel interpolation in luminanee. As for chrominance component, the architecture uses shift＆add to calculate eight-pixel interpolation. The experimental results show that the architecture proposed in this paper can meet the requirement of HD and CIF image and it can consumes less resources.

关 键 词：H.264标准 1/4精度内插 硬件实现结构 

分 类 号：TN919.81[电子电信—通信与信息系统]