基于Cadence异步时序电路分析与仿真  

Asynchronous Timing Circuit Analysis and Simulation Based on Cadence

作　　者：乔正盛[1] 李建武[1] 

机构地区：[1]华中光电技术研究所,湖北武汉430074

出　　处：《机电产品开发与创新》2008年第6期144-145,176,共3页Development & Innovation of Machinery & Electrical Products

摘　　要：探讨了在信号完整性分析中的异步时序电路的时序图及时序关系式,并结合具体的设计实例,计算出满足关系式的时序区间,最后在Cadence下进行了信号完整性仿真,验证了设计的时序匹配性,为高速PCB异步时序电路设计提供了一种分析与设计方法。The thesis discussed the timing maps and formulas of asynchronous time circuit when analyzing it signal integrality. And based on an example designed, the paper figured out timing sector meeting related formula, last simulated the signal integrality of the example, validated if the design matched its timing. It provided a analysis and design method to design asynchronous timing circuit on high speed PCB.

关 键 词：异步时序电路 电路分析 建立时间 保持时间 仿真 

分 类 号：TN7[电子电信—电路与系统]