一种脉冲信号载波频率同步环及FPGA实现  

Pulse carrier frequency synchronization loop and its FPGA implementation

作　　者：张江林[1] 吕善伟[1] 董胜波[2] 韦志棉[1] 

机构地区：[1]北京航空航天大学,北京100083 [2]中国航天科工集团公司二院二十五所,北京100854

出　　处：《系统工程与电子技术》2008年第11期2050-2053,共4页Systems Engineering and Electronics

基　　金：国防预研基金资助课题(513250504)

摘　　要：针对脉冲信号载波频率的同步问题,提出一种快速高精度的数字锁频环路。该环路采用改进的相位差分频率估计算法进行快速载波频率粗估计,其信噪比阈值低于Kay法,在信噪比偏低时也能达到Cramer-Rao界。应用数字下变频技术和Kay算法实现载波频率的精确估计。设计实例的仿真结果表明了该环路的有效性,环路可在短时间内完成高精度的载波频率同步。To aim at pulse signals carrier frequency synchronization, a rapid and high accurate digital frequency-locked loop is proposed. In this loop, an effective single frequency estimator based on the differential phase measurements is employed to perform rapid carrier frequency initial coarse estimation, it attains the Cramer-Rao bound （CRB） down to lower signal to-noise ratio （SNR） values compared with the Kay＇s method. Digital down conversion and Kay＇s method are adopted to perform carrier frequency accurate estimation. Simulation results of an example are included to illustrate the performance of the proposed loop, high accurate carrier frequency synchronization can be accomplished within a shorter time.

关 键 词：载波同步 频率估计 脉冲信号 数字锁频环 

分 类 号：TN911.23[电子电信—通信与信息系统]