高精度低功耗多位量化∑-Δ调制器的设计  

Design of a high resolution low power multi-bit Σ-Δ modulator

作　　者：欧伟[1] 吴晓波[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《机电工程》2008年第12期27-30,共4页Journal of Mechanical & Electrical Engineering

基　　金：国家自然科学基金资助项目(90207002);浙江省自然科学基金资助项目(Z104441)

摘　　要：为了解决目前音频应用模数转换器(ADC)功耗过大的问题,提出了模数转换器低功耗设计的目标。在系统设计方面,合理选择过采样率、调制器阶数、量化位数,保证了在满足性能要求的情况下优化信号最大输入幅度和功耗;在考虑各种非理想因素的影响时,结合Simulink进行了详细的验证,获得了功耗优化的模块指标;在电路设计上部分模块采用了新结构,简化了电路模块构成,相应地减小了功耗。通过SPICE仿真得到调制器的功耗降低至200μW左右,证明了此设计达到了低功耗的优化目的。In order to tackle the power hungry problem of most existing analog-to-digital converter（ADC） , the power optimization aim at data converters was put forward. A reasonable combination of oversampling ratio, order and effective bit of quantizer was chosen to optimize requirement of the maximum input signal range and minimum power consumption. Simulink was employed for the nonideality analysis of circuits and reasonable specification of building blocks was chosen while considering low power requirement. In circuit implementation some building blocks were realized in new topology with reduced blocks and simplified design, which also minimize the power requirement. Through the SPICE simulation, the modulator consumed power is only about 200 μW, and it proves the efficiency of the power optimization on modulator design.

关 键 词：∑-△调制器 多位量化 DWA 低功耗 音频 模数转换器 

分 类 号：TN792[电子电信—电路与系统]