音频专用DSP核的硬件循环设计  

Design of Hardware Loops for Audio-Specific DSP Core

作　　者：李辉[1] 李平[1] 王忆文[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2008年第6期851-854,共4页Microelectronics

摘　　要：介绍了一个音频专用DSP核的硬件循环设计。该设计能实现单条指令和多条指令的硬件循环,并且由同一个电路实现,具有相同的指令格式,并支持最多4重嵌套的硬件循环。基于FPGA开发平台进行实验验证,结果表明,该设计能够正确高效地实现循环操作,为音频专用DSP核实现音频解码提供必要的支持。Design of hardware loops for an audio-specific DSP core was presented, which could implement both single-instruction and multi-instruction hardware loops with the same hardware architecture and loop instructions, and up to 4 nested loops were allowable. The proposed design was verified based on FPGA platform. It has been demonstrated that the hardware loop architecture can perform repetitive execution of instructions accurately and efficiently. The design provides necessary support for audio decoding based on audio-specific DSP core.

关 键 词：音频解码 数字信号处理器 硬件循环 FPGA AC-3 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]