达林顿晶体管的PSpice建模和仿真  

PSpice Modeling and Simulation of Darlington Transistor

作　　者：陶春见[1] 林青 

机构地区：[1]上海交通大学,上海200030 [2]英特尔产品上海有限公司,上海200131

出　　处：《山西电子技术》2008年第6期18-19,共2页Shanxi Electronic Technology

摘　　要：达林顿晶体管的PSpice建模优化是在室温下完成的,一些典型的NPN达林顿对的电子特征是基于芯片TIP120仿真的,比如在不同的集电极-射极饱和电压状态下的电流增益(hFE),集电极电流vs,输入级电流,以及集电极-射极饱和电压和集电极电流之间的关系。The PSpice model of a Darlington transistor is extracted and optimized in room temperature, some typical electrical characteristics of NPN Darling＇ton pair based on Chip TIP120 are simulated, such as current gain （hFE）, collector current vs. input current under the condition of different collector-emitter saturation voltage, and also the relationship between collector-emitter saturation voltage and collector current.

关 键 词：PSpice建模 达林顿晶体管 电流增益 集电极电流 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]