新型高速低功耗动态比较器  

Novel High-Speed Low-Power Dynamic Comparator

作　　者：林武平[1,2] 郭良权[1,2] 于宗光[1,2] 黄召军[1,2] 

机构地区：[1]江南大学,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《半导体技术》2008年第12期1119-1122,1147,共5页Semiconductor Technology

基　　金：江苏省自然科学基金资助项目(BK2007026)

摘　　要：基于预放大锁存理论,提出了一种新型高速低功耗动态比较器。该比较器采用预放大级、动态锁存器及输出缓冲级构成的三级结构,与传统比较器不同,该比较器采用了一种新型动态结构作为输出缓冲级以实现高速低功耗。在CSMC 0.5μm/5 V Si CMOS工艺模型下,采用Hspice对电路进行模拟。结果表明在100 MHz的时钟下,精度可达0.2 mV,功耗仅为1.12 mW。Based on preamplifier-latch theory, a new structure and high-speed low-power dynamic comparator was presented. A three-stage structure consisting of a preamplifier, a dynamic latch and an outputbuffer were adopted in this comparator. In order to realize high-speed and low-power, a new dynamic structure was used as output-buffer, which is different form traditional comparator. Based on CSMC 0.5 gin/5 V Si CMOS model, the circuit was simulated by Hspice. The results show that it can distinguish 0.2 mV at 100 MHz, and power consumption is only 1.12 roW.

关 键 词：动态比较器 正反馈 差分放大器 高速低功耗 

分 类 号：TN431[电子电信—微电子学与固体电子学]