一种通用分频器的设计与CPLD实现  

Design and CPLD Realization of a Universal Frequency Divider

作　　者：程耀林[1] 

机构地区：[1]中南民族大学电子信息工程学院,武汉430074

出　　处：《中南民族大学学报（自然科学版）》2008年第4期76-79,共4页Journal of South-Central University for Nationalities：Natural Science Edition

摘　　要：提出了一种通用分频器的设计与采用CPLD实现的方法,该分频器有较强的通用性,使用方便,它只有一个控制信号即分频比,分频比大小没有限制、可调,无论分频比为奇数或者偶数时,其分频时钟都可实现均匀(即等占空比).给出了设计方案及其原理,提供了一个CPLD设计实例,使用了Verilog-HDL语言进行设计,并在MAX+PLUS软件上进行了仿真,提供了仿真结果和占空比公式,仿真结果表明:这种分频器是可以实现的.This paper introduces design and CPLD realization of a universal frequency divider with a well universality and useable characteristic. It has only one control signal： dividing ratio, Its value is variable and incapable of limiting, and is weather even or odd, dividing clock is all uniform（namely its duty is 50%）. design scheme and principle is provided, and a CPLD design example is also provided, Verilog _HDL is used in the design, and simulated on MAX ＋PLUS Ⅱ software platform, then simulation result and duty formula is provided,it indicates that this frequency divider can be realized.

关 键 词：分频器 可调分频比 等占空比 复杂可编程逻辑器件 

分 类 号：TN911.72[电子电信—通信与信息系统]