High performance word level sequential and parallel coding methods and architectures for bit plane coding  

作　　者：XIONG ChengYi TIAN JinWen LIU Jian 

机构地区：[1]College of Electronic Information Engineering, South-Central University for Nationalities, Wuhan 430074, China [2]Institute of Pattern Recognition & Artificial Intelligence, Key Laboratory of Education Ministry for Image Processing and Intelligent Control, Huazhong University of Science & Technology, Wuhan 430074, China

出　　处：《Science in China(Series F)》2008年第4期337-351,共15页中国科学（F辑英文版）

基　　金：the Natural Science Foundation of Hubei Province (Grant No. 2006ABA370);Civil Research Project of State Defense (Grant No. C1120061304);National Natural Science Foundation of China (Grant No. 60572048);National High Technology Research and Develop-ment of China (863 Program) (Grant No. 2004AA119010-6)

摘　　要：This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.

关 键 词：bit plane coding high performance word-level sequential multi-word parallel 

分 类 号：TN47[电子电信—微电子学与固体电子学]