一种快速傅里叶变换算法的FPGA实现  

Implementation of a Fast Fourier Transform Algorithm Based on FPGA

作　　者：蒋华[1] 

机构地区：[1]南通大学电子信息学院,江苏南通226019

出　　处：《信息与电子工程》2008年第6期444-447,共4页information and electronic engineering

基　　金：江苏省高校自然科学基础研究资助项目(06KJB510089);江苏省南通大学自然科学基金资助项目(07Z041);江苏省南通市应用研究计划资助项目(K2008015)

摘　　要：分析了快速傅里叶变换(FFT)算法的4种典型结构,提出了一种采用按时间抽取的基2单蝶形运算单元递归结构。对一种64点FFT进行仿真验证,在Cyclone的EP1C6T144C7上实现共占用967个逻辑单元,最高频率达56.47MHz。通过降低蝶形运算单元中乘法数目和采用乒乓RAM结构,节约了硬件资源,加快了FFT运算速度。Based on the analysis of four kinds of typical structure of Fast Fourier Transform（FFT） algorithm, a recursive structure of FFT on radix-2 single butterfly processing element sampled by time is presented. A 64 points FFT is implemented on the Cyclone EPIC6T144C7 device. The result of the simulation shows that the resource consumption requires 967 logical elements and the top frequency can reach 56.47 MHz. Through reducing the multiplication number of butterfly processing elements and using ping-pang RAM structure, less hardware resource requirement and high speed is obtained.

关 键 词：快速傅里叶变换 现场可编程门阵列 基2 乒乓RAM 

分 类 号：TN791[电子电信—电路与系统]