高可靠8051微处理器的设计与实现  

Design and Implementation of a High-Reliability 8051 Microprocessor

作　　者：赖鑫[1] 戴葵[1] 刘芳[1] 王志英[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2009年第1期117-120,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60603062);湖南省自然科学基金资助项目(06jj30035)

摘　　要：本文介绍了一款高可靠8051(HR8051)的设计与实现。在一款现有高性能8051微处理器体系结构的基础上,针对单粒子翻转事件(SEU),应用各种可靠性增强技术,如时空三模冗余(ST-TMR)、控制流检测、安全状态机等,并对可靠性增强后的处理器进行故障注入,以验证其可靠性增强效果。故障注入结果表明,采用了可靠性增强技术后,处理器的可靠性有了很大的提高。This paper describes the design and implementation of a high-reliability 8051 microprocessor （HR8051）. Based on the existing high-performance 8051 microprocessor architecture, the HR8051 microprocessor has been hardened by several reliability-improving technologies, e.g. space-time triple modular redundancy（ST-TMR） ,control flow checking,safe state machine, and so on, to mask the SEU（single event upset）event. In order to check how much reliability the hardened microprocessor can achieve, fault injection is applied. The final results indicate that the reliability of the HR8051 micropro- cessor is improved significantly.

关 键 词：高可靠微处理器 时空三模冗余 可靠性增强技术 故障注入 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]