异步子字并行乘累加单元的设计与实现  

Design and Implementation of the Asynchronous Sub-Word Parallel MAC Unit

作　　者：王友瑞[1] 王蕾[1] 石伟[1] 戴葵[1] 王志英[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2009年第1期121-124,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(90407022);国家863计划资助项目(2007AA01Z101)

摘　　要：异步电路能很好地解决同步集成电路设计中出现的时钟扭曲和时钟功耗过大等问题。本文采用异步集成电路设计方法设计了一款32位异步子字并行乘累加单元,并在0.18μm工艺条件下实现了该单元。通过使用特殊的部分积译码电路,该乘累加单元能支持多种子字并行模式,适用于多媒体处理。评测结果表明,异步乘累加单元的性能和功耗指标均优于采用同样结构的同步乘累加单元。The problems such as clock skew and high power consumption may exist in synchronous integrated circuit design, which can be well solved in asynchronous design. A 32-bit asynchronous sub-word parallel MAC unit in adopting the asynchronous integrated circuit design method is presented in this paper. And it is implemented in the 0. 18μm process. The MAC unit we design supports various sub-word parallel models using a special partial product decode circuit. It is suitable for multimedia processing. The test results indicate the performance and power consumption of this asynchronous MAC unit are superior to the synchronous counterpart.

关 键 词：异步 子字并行 乘累加 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]