片上网络的互连问题及解决措施综述  

Survey on Interconnects of Networks-on-Chip and its solutions

作　　者：谢国梁[1] 凌翔[1] 胡剑浩[1] 

机构地区：[1]电子科技大学通信抗干扰技术国家级重点实验室,四川成都610054

出　　处：《中国集成电路》2009年第1期38-43,共6页China lntegrated Circuit

基　　金：863项目资助(2007AA01Z291)

摘　　要：在大规模集成电路工艺的深亚微米时代,片上网络(NoC)互连总线遭遇了来自三个方面的威胁:功耗、传输延时、可靠性,它们已经成为限制NoC性能提高的瓶颈。鉴于总线编码的灵活性和综合处理能力,本文首先分析了多种分别针对功耗、延时、可靠性问题的总线编码处理方案,最后介绍了一种统一的总线编码框架来综合处理这三方面的挑战。Interconnect buses in deep-submicron network-on-chip （ NoC ） designs suffer from three major problems： power dissipation, propagation delay, reliability, and all of the three problems have become bottlenecks of NoC performance improvement. Taking into account flexibility and comprehensive ability of bus coding, this paper firstly discusses bus coding for power, delay, and reliability respectively. And finally introduces a unified bus coding framework to answer these challenges as a whole.

关 键 词：片上网络 总线延时 总线编码 功耗 可靠性 

分 类 号：TN47[电子电信—微电子学与固体电子学]