高速可配置RSA密码协处理器的ASIC设计  

ASIC design of a high-speed reconfigurable RSA cryptography coprocessor

作　　者：曹威[1] 

机构地区：[1]同济大学微电子中心,上海200092

出　　处：《电子技术应用》2009年第1期43-46,共4页Application of Electronic Technique

摘　　要：提出了一种基于嵌入式系统的高速、可配置RSA密码协处理器的ASIC设计方案,可实现256bit到2048bit的RSA加密运算。为了提高运算速度,采用改进的高基模乘算法和流水线结构;为了消除协处理器与内存之间的通信速度瓶颈,使用DMA直接访问方式;同时,数据输入输出都使用双口存储体,形成加解密数据流,本文将该加解密协处理器简称为SPU(Streaming Processing Unit)。In this paper, an ASIC design of a high-speed reconfigurable RSA cryptography coprocessor is presented. It can implement RSA encryption/decryption from 256 bit to 2 048 bit. In order to speed up the operation, an advanced high radix module multiplication algorithm and pipeline architecture is presented. With the purpose of removing performance bottlenecks caused by the transfer of data between coprocessor and external RAM, we adopt direct memory access（DMA） mode. At the same time, a local memory with dual ports is used to form data streaming. So the RSA cryptography coprocessor is also named SPU in this paper.

关 键 词：RSA 模乘算法 蒙哥马利乘法 专用集成电路 加解密协处理器 

分 类 号：TN409[电子电信—微电子学与固体电子学]