基于AVS的变字长解码器的设计及其FPGA验证  

Design of variable length decoder for AVS and it′s implementation on FPGA

作　　者：李晓燕[1] 张卫宁[1] 袁鲲[1] 赵建全[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2009年第1期53-56,62,共5页Application of Electronic Technique

摘　　要：提出了一个完整的AVS变字长解码器的硬件架构,在设计中采用加入FIFO的方法构成流水结构,并尽量减少变字长解码器中各子模块的运行节拍,大大提高了系统的运行速度。本设计已经通了FPGA验证。该变字长解码器不仅可以成为其他AVS解码器的硬件加速器,同时由于视频编解码标准的相似性,稍加改动即可应用在其他的视频标准中。This paper proposes an entire VLD hardware architecture for AVS. It uses FIFO to make the pipeline architecture, and reduces the runtime of each submodule of VLD, so it obviously improves the working speed of the entire system. This design has been verified by FPGA.This VLD not only can be used as an accelerator for other AVS decoders but also can be used in other video standard with a little changed because of the comparability of all the video standards.

关 键 词：AVS 变字长解码器 FPGA 

分 类 号：TN919.8[电子电信—通信与信息系统]