耦合结构高分辨率电荷按比例缩放DAC的分析  

Analysis of Coupled High-resolution Charge Scaling DAC

作　　者：刘会刚[1] 耿卫东[1] 高丕涛[1] 

机构地区：[1]南开大学天津市光电子薄膜器件与技术重点实验室,天津300071

出　　处：《南开大学学报（自然科学版）》2008年第6期49-53,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：天津市自然科学基金(033600711);天津市科委攻关项目(033187011)

摘　　要：耦合结构高分辨率电荷按比例缩放DAC占用面积小,功耗低,然而其互连结点之间的寄生电容影响了它的线性.介绍了耦合结构高分辨电荷按比例缩放DAC级间耦合电容值的设计方法,讨论了寄生电容对DAC精确度的影响.用两种不同的理论模型分析了电容轨迹误差对DAC精确度的影响,并在两种模型下比较了两级和传统的单级电荷按比例缩放DAC的精确度和版图面积.Coupled high-resolution charge scaling DAC had small area and low power consumption. However, the parasitic capacitances on the interconnecting nodes of charge scaling DAC restricted the linearity of the DAC. A method to design the value of coupling capacitor in coupled high-resolution charge-scaling DAC is presented. It also discusses the impact of parasitic capacitance on DAC. Two different models are used to analyzing the impact of capacitor tracking error on DAC＇s accuracy. The potential accuracy and area of the two-stage charge scaling DAC and the conventional single-stage approach are compared in these models.

关 键 词：寄生电容 耦合电容 电容轨迹误差 电荷按比例缩放DAC 

分 类 号：TN27[电子电信—物理电子学]