高速数据采集系统设计  

Design of High Speed Data Acquisition System

作　　者：张俊杰[1] 章凤麟[1] 叶家骏[1] 

机构地区：[1]上海大学特种光纤与光接入网教育部重点实验室,上海200072

出　　处：《计算机工程》2009年第1期207-209,212,共4页Computer Engineering

基　　金：国家自然科学基金资助项目"基于骨骼肌结构形态信息的假手控制与建模研究"(60701021);上海市优秀青年教师基金资助项目(2005);上海市重点学科建设基金资助项目(T0102)

摘　　要：为满足雷达信号采集的要求,设计一个12 bit 100 MS/s的基于PCI总线的数据采集系统。该系统能够实现6GB数据的实时采集与存储。可编程逻辑器件控制数据的采集、存储与传输。PCI数据传输采用PCI主模式,传输速率达到60MB/s,采集信号的信噪比达到55dB(30MHz模拟信号)。A 100 MS/s data acquisition system based on PCI bus is designed to meet the need of high-speed radar signal sampling. The 6 GB sampling ADC data can be saved on this card and transferred to the computer simultaneously, which is controlled by one FPGA chip. The transfer rate between this card and the computer can reach up 60 MB/s. The SNR of the sampled data can reach 55 dB at 30 MHz.

关 键 词：PCI控制器 可编程器件 抖动 信噪比 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]