WorldFIP智能主站的开发  

Development of intelligent WorldFIP master

作　　者：翟伟翔[1] 白焰[1] 高峰[1] 

机构地区：[1]华北电力大学自动化系,北京102206

出　　处：《电力自动化设备》2009年第2期121-124,152,共5页Electric Power Automation Equipment

摘　　要：根据WorldFIP的分布式测控系统的基本结构,提出了以ARM9和VxWorks为软硬件平台、具有快速以太网接口的WorldFIP智能主站的设计方案。硬件由以ARM9处理器AT91RM9200为核心的嵌入式主板模块和WorldFIP通信接口模块组成,模块间的时序匹配由复杂可编程逻辑器件(CPLD)实现,时序转换逻辑用硬件描述语言VHDL设计,同时提供核心代码。驱动软件部分,解析了FDM库的UML静态结构。并给出了在VxWorks下的移植步骤;用户层方面,以应用时间同步、从站设备识别、从站服务代理3个模块为例介绍系统管理软件工作原理与实现方法,利用VxWorks的任务控制、队列、时钟、信号量、事件等实现任务间调度与通信;网关服务器软件则分析了双缓冲对列、socket服务器程序和WorldFIP用户层接口。实验证明该主站工作稳定可靠,且开放性、实时性、运算执行能力良好。According to the basic architecture of WorldFIP-based distributed supervision and control system, an intelligent WorldFIP master with FastEthernet interface is designed based on ARM9 and VxWorks platform. The hardware is composed of two parts, the main board with embedded microprocessor AT 91RM9200 and the WorldFIP communication module. The time sequence matching between two modules is designed with VHDL program on CPLD（Complex Programmable Logic Device） chip and the key codes are given. For the bus arbitrator driver, the UML static structure of FDM（FIP Device Manager） library is analyzed and its transplant steps under VxWorks are presented. On the user layer, the principle and implementation of system management software are illustrated by the modules d application time synchronization, slave device identification and slave device service agent. The task schedule and communication are realized by the task control, queue, clock, semaphore and event of VxWorks. For the gateway server, the double buffeting queue, socket server and interface with WordFIP user- layer are described. Experiment proves that the master is reliable and stable, with the excellent performances in openness, speed and computing capability.

关 键 词：主站 总线仲裁器 网关 VXWORKS WordFIP 智能 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]