可重构多路仲裁器  

Design of reconfigurable multi-way arbiter

作　　者：姜晶菲[1] 唐玉华[1] 崔向东[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与设计》2009年第1期1-3,215,共4页Computer Engineering and Design

基　　金：国家自然科学基金项目(NSFC60736013)

摘　　要：多路仲裁器的设计不仅涉及到协议实现,还必须考虑复杂的时序控制,根据具体应用的不同设计的特异性较强。提出了模块化的可重构多路仲裁器结构并进行了具体设计。可重构多路仲裁器能够进行仲裁逻辑的动态重构,可方便地适应不同规模和复杂度的通信要求,并规则地解决了异步时钟域信号转换的问题,使得仲裁器具有一定的可变性和快速实现性,其设计模式能适应较大范围接口应用。Both the protocol and the complicated logic timing must be considered in the multi-way arbiter design. Arbiter circuits of different applications show many particularities. Reconfigurable arbiter can support dynamic reconfiguration using the FPGA technology. The methods of parameterization and modularization are used in the arbiter design to support reconfiguration. The problem of signal translation between two different clock fields is solved in regular way. The reconfigurable arbiter is more flexible and is implemented quickly. Its model can suit for more interface design.

关 键 词：FPGA 动态重构 仲裁器 异步时钟域 通信 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]