一种128位高精度浮点乘加部件的研究与实现  

Research and Realization of a 128-Bit Multiply-Add-Fused Unit

作　　者：张峰[1] 黎铁军[1] 徐炜遐[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2009年第2期93-96,103,共5页Computer Engineering & Science

摘　　要：高性能高精度的浮点数值处理一直是科学计算追求的目标。为此,本文研究并实现了一种128位浮点乘加融合计算单元。在乘法模块中,使用分块乘法,复用57位乘法模块,减小了数据宽度。采用三输入前导1预期技术,简化了预编码,缩短了预测电路的延时并减小面积。该模块单元使用Verilog语言实现,用Design Compiler进行逻辑综合,在simc0.13μm工艺下频率达202MHz,关键路径延时为4.93μs,面积约为191000门。High-performance and high-precision floating-point processing has been the object of scientific computing. This paper propgses the design of a 128-bit fused multiply-add unit. In the multiplication module reuse of the 57bit multiplication modules, the width of the data is reduced. This enhanced multiply-add-fused unit needs a LOP circuit to deal with three operands, simplify the encoding, shorten the delay and reduce the circuit size. The synthesis result shows that the design can work at 202MHz, the data arrival time is 4. 93μs, the area is 191,000 gates.

关 键 词：乘加融合 三输入前导1预测 浮点部件 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]