一种低功耗射频CMOS电荷泵锁相环的设计  

A Low-Power RF CMOS Charge Pump PLL

作　　者：周海峰[1] 韩雁[1] 董树荣[1] 韩晓霞[1] 程维维[1] 

机构地区：[1]浙江大学微电子与光电子研究所,杭州310027

出　　处：《微电子学》2009年第1期49-52,57,共5页Microelectronics

基　　金：国家高技术研究发展(863)计划基金资助项目(2008AA04Z309)

摘　　要：描述了基于P型CSL(Current Steer Logic)架构压控振荡器的低功耗射频锁相环设计。其鉴频鉴相器模块采用预充电模式,具有高速、无死区等特点;电荷泵模块在提高开关速度的基础上,改进了拓扑结构,使充放电电流的路径深度相同,更好地实现了匹配;为了达到宽调谐范围的目的,电荷泵模块采用1.8 V电源电压,而压控振荡器模块采用3.3 V,这样可充分利用电荷泵的输出电压范围实现宽调谐。电路设计基于0.18μm 1P6M CMOS工艺,芯片实测结果显示,锁相环工作在940 MHz^2.23 GHz的频率范围内,功耗低于15.2 mW,芯片面积为750μm×400μm(不包括IO)。A phase-locked loop （PLL） based on voltage controlled oscillator （VCO） with P-type CSL （Current Steer Logic） structure was presented. A pre-charge mode was used in phase/frequency detector to realize high speed and dead zone free, etc. The topology of the circuit was also enhanced to equalize the depths of charge and discharge currents, which improved the circuit matching. In order to expand the tuning range of the PLL, a 1.8 V power supply was used in the charge pump module, while a 3.3 V power supply was used for VCO module. This circuit was implemented in a 0. 18um IP6M CMOS technology, and the core chip occupied an area of 750um × 400 um . Test results showed that the PLL operated in the frequency range between 940 MHz and 2. 23 GHz, with a power consumption less than 15.2 nW.

关 键 词：锁相环 射频 压控振荡器 电荷泵 

分 类 号：TN402[电子电信—微电子学与固体电子学]