一种四阶锁相频率合成器的环路设计  

Design of Fourth-Order PLL Synthesizer

作　　者：薛昀[1] 

机构地区：[1]桂林电子科技大学信息科技学院,广西桂林541004

出　　处：《桂林电子科技大学学报》2009年第1期19-21,共3页Journal of Guilin University of Electronic Technology

摘　　要：重点讨论了四阶锁相频率合成器的环路滤波器的设计。环路滤波器主要采用有源比例积分滤波器,为获得更好的环路性能,采用了三阶环路滤波器。通过环路开环传递函数,得到了环路的时间常数和环路滤波器的元件的设计公式。对环路进行了仿真实验,实验结果和实际测试表明总体性能较好,能满足项目要求。We introduced a fourth-order PLL synthesizer with emphasis on active loop filter （LF） in our work, which is constructive for improving the performance of PLL. The fourth-order loop restricts phase noise greatly by a third-order LF. We approached open-loop phase transfer function, evaluation formulae for parts of LF, and parameter time. The PLL synthesizer model was simulated and found to be credible. The synthesizer is tested to be satisfied.

关 键 词：四阶锁相环 波特图 相位裕量 

分 类 号：TN914[电子电信—通信与信息系统]