High-performance hardware architecture of elliptic curve cryptography processor over GF(2^(163))  

作　　者：Yong-ping DAN Xue-cheng ZOU Zheng-lin LIU Yu HAN Li-hua YI 

机构地区：[1]Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

出　　处：《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》2009年第2期301-310,共10页浙江大学学报（英文版）A辑（应用物理与工程）

基　　金：supported by the Hi-Tech Research and Development Program (863) of China (No. 2006AA01Z226);the Research Foun dation of Huazhong University of Science and Technology, China (No. 2006Z001B)

摘　　要：We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF（2^163） in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexⅡ XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF（2^163） in 34.11 μs, occupying 2821 registers and 13 376 LUTs.We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF(2163) in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit,which includes an addition unit,a square and a carefully designed multiplication unit. In the proposed architecture,multiplication,addition,and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexII XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF(2163) in 34.11 μs,occupying 2821 registers and 13 376 LUTs.

关 键 词：Elliptic curve cryptography （ECC） Scalar multiplication Hardware implementation 

分 类 号：TN402[电子电信—微电子学与固体电子学]