考虑通孔电阻和耦合电容的时延驱动的层分配算法  

Timing Driven Layer Assignment Considering Via Resistance and Coupling Capacitance

作　　者：贾艳明[1] 蔡懿慈[1] 洪先龙[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《计算机辅助设计与图形学学报》2009年第2期196-202,共7页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(60776026)

摘　　要：针对集成电路设计的多层布线问题,提出了以直接优化互连时延为目标、同时考虑通孔电阻与耦合电容的层分配算法.通过基于路径的时延分析寻找电路的关键路径,以通孔的时延模型和概率耦合电容模型作为层分配模型计算资源分配的代价,利用基于启发式的贪婪算法进行层分配.实验结果表明:该算法比只控制通孔和耦合电容数量的层分配策略具有更大的优势.Aiming at optimizing interconnect timing directly, assigning proper routing layer resource and considering via-induced-delay and coupling-induced-delay simultaneously, a timing driven layer assignment algorithm for multilayer routing problem is proposed. This algorithm includes three phases： first, path based timing analysis is applied to find the timing-critical part of a circuit. Then a via aware timing model and a probabilistic coupling capacitance model are used to calculate the cost of assigning a net to a routing layer. Finally a greedy algorithm is used to perform layer assignment. Experimental results show that, it is necessary to optimize timing directly instead of merely controlling the amount of vias and couplings.

关 键 词：层分配 时延驱动 通孔电阻 耦合电容 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]