低抖动时钟锁相环设计  

Design of a Low Jitter Phase Locked Loop

作　　者：尹海丰[1] 毛志刚[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《固体电子学研究与进展》2008年第4期564-568,共5页Research & Progress of SSE

摘　　要：采用SMIC0.13μm CMOS工艺,设计实现了一个基于自偏置技术的低抖动时钟锁相环。锁相环核心功耗约为8.4～16.8mW,可稳定输出的频率范围为25MHz～2.4GHz,测试结果显示,锁相环锁定在1.36GHz时输出时钟的均方抖动为2.82ps,周期峰峰值抖动为21.34ps。A low jitter phase locked loop based on self-biased technology is designed and fabricated in SMIC 0. 13um CMOS process. The power consumption of the PLL core is about 8.4 to 16.8mW, and the output frequency range is 25 MHz to 2.4 GHz. Test result shows that the rms jitter is 2.82 ps and the peak-to-peak jitter is 21.34 ps when PLL is locked on 1.36 GHz.

关 键 词：锁相环 鉴频鉴相器 电荷泵 压控振荡器 可编程分频器 

分 类 号：TN75[电子电信—电路与系统]