一种带锁相环的多模式时钟发生电路设计  

Design of a Multi-mode Clock Generator with a PLL

作　　者：宋爽[1] 赵梦恋[1] 陈海[1] 吴晓波[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,杭州310027

出　　处：《固体电子学研究与进展》2008年第4期569-574,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(90707002);浙江省自然科学基金资助项目(合同号Z104441)

摘　　要：为提高开关电源控制芯片使用灵活性,优化对开关电源效率、纹波等性能的控制,并方便噪声滤除,提出一种带锁相环的多模式时钟发生电路芯片的设计。该电路可提供选择1.7MHz或2.6MHz的固定频率模式或锁相范围500kHz～3MHz的外部输入模式,应用于开关电源控制芯片时,可根据开关电源的应用情况设置工作频率,达到性能最佳化。该芯片已在1.5μmBCD(Bipolar-CMOS-DMOS)工艺下设计完成。测试结果表明芯片工作正常,预期的功能均已实现,可作为模拟电路IP使用。A multi-mode clock generator with a phase locked Loop （PLL） was proposed to enhance flexibility of switch mode power supply （SMPS） control IC and optimize its control performance, which is beneficial to the high efficiency, low voltage ripples and noise of SMPS. This clock generator provides 1.7 MHz/2.6 MHz fixed frequency mode and external input mode with a locked range from 500 kHz to 3 MHz. Applied to SMPS control IC, it enabled the users to set the operation frequency of SMPS to achieve performance optimization according to its applications. The chip was designed and fabricated in 1.5 um BCD technology. Test results showed that the chip worked well and all expected functions were successfully realized. It can be used as an analog circuit IP and applied to different SMPS controller ICs.

关 键 词：开关电源控制芯片 时钟发生电路 锁相环 固定频率模式 外部输入模式 

分 类 号：TN433[电子电信—微电子学与固体电子学]