一种高性能分簇式超标量微处理器结构  

A High-Performance Clustered Superscalar Microprocessor Architecture

作　　者：甘初晖[1] 杨兵[1] 喻明艳[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《微处理机》2008年第6期39-42,共4页Microprocessors

摘　　要：随着超标量微处理器指令发射宽度的增大,流水线中各个部件的硬件复杂度以及连线长度迅速增加,特别是当工艺线宽越来越小时,连线延迟成为阻碍处理器性能提高的瓶颈。我们提出了一种分簇式超标量处理器结构,在维持发射宽度不变的前提下能够有效降低硬件复杂度,缩短连线长度,减小延迟时间。通过对该分簇的处理器进行模拟并估算它们的物理寄存器组的延迟和面积,我们发现,对于2×4分簇结构,在寄存器组面积减少12%的同时,处理器性能至少可获得16%的提升。As the instruction issue widths of superscalar microprocessors increase, hardware complexities of components in pipeline grow rapidly,and wires become longer as well. Especially when the technology feature size scales, wire delay becomes the bottleneck that encumbers the improvement of processorperformance. In this paper we brought forward a clustered superscalar architecture, which could effectively reduce hardware complexity, shorten wire lengths, and bring down wire delays without affecting issue widths. By simulating the proposed clustered architectures and estimating their physical register files, we found that not only the register file area reduces by 12% ,but also the performance improves by 16% at least for 2 × 4 configuration.

关 键 词：分簇 超标量 微处理器 寄存器组 

分 类 号：TN402[电子电信—微电子学与固体电子学]