可变长数据全并行FFT地址生成方法  

A strategy of address generating for Programmable high throughout FFT processor

作　　者：刘红侠[1] 黄巾[1] 黄士坦[1] 

机构地区：[1]西安微电子技术研究所,西安710075

出　　处：《信号处理》2009年第2期185-193,共9页Journal of Signal Processing

基　　金：国防"十一五"预先研究项目(513160202)

摘　　要：本文通过对混合基4/2 FFT算法的分析,在优化采样数据、旋转因子存储及读取方法的基础上,提出了将N= 2~m点,m为奇、偶两种情况的地址产生统一于同一函数的算法,并设计了简单的插入值产生及快速插入位置控制电路,从而用一个计数器、同一套地址产生硬件,通过简单的开关模式控制,可实现任意长度FFT变换的地址产生单元,该地址产生单元在一个时钟周期内产生读取所需旋转因子及并行访存4个操作数的地址。本文设计的FFT处理器每周期完成一个基4或2个基2蝶式运算,在吞吐率高、资源少的基础上实现了处理长度可编程的灵活性,同时避免了旋转因子重复读取,降低功耗。Through analyzing the mixed-radix 4/2 FFT algorithm and optimizing the method of storage and accessing sampling da- ta and twiddle factors,a same mixed-radix 4/2 address generating function for whatever m is odd or even,which m =log2N and N is the length of FFT, is proposed. At the same time, a simple insert value generating circuit and a fast insert location control circuit are designed. As a result, the addresses of any FFT length can be generated with only one counter and one set of address generating hardware controlled by a switch. The address generator designed in this paper can generate the addresses of twiddle factors and four operands needed in one cycle. The FFT processor described can execute one radix-4 or two radix-2 butterfly operators in one cycle. Therefore,it has wide applicability and high throughout with less area than any other similar designs. Moreover, it has low power consumption by avoiding reading twiddle factors repeatedly.

关 键 词：快速傅利叶变换(FFT) 混合基4/2蝶形单元 地址发生器 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]