基于JTAG和FPGA的嵌入式SOC验证系统设计与实现  

Design of the embedded SOC verification system based on JTAG and FPGA

作　　者：窦建华[1] 孙强[1] 陆俊峰[2] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009 [2]中电集团第38研究所,安徽合肥230031

出　　处：《合肥工业大学学报（自然科学版）》2009年第3期336-339,共4页Journal of Hefei University of Technology：Natural Science

摘　　要：文章设计采用FPGA、NIOSⅡ软核以及定制的JTAG逻辑,构建了一种通用的FPGA嵌入式验证平台,成功地完成了国产某型DSP芯片的验证与测试。此验证系统首次建立了从PC到验证目标系统的完整的数据链路,解决了SOC验证系统的可重用性和验证数据发送、传输、采集的实时性、准确性及可测性问题。The presented design adopts the FPGA, the Nios Ⅱ soft core and the customized JTAG logic, and a universal FPGA embedded verification system is established. By using the verification system, a DSP chip made in China is verified. This system first sets up a complete data stream between the PC and the targeted system in a flew way. The design solves the problems of the real-time, accurate and predictable sending , transmission and collection of verified data as well as the reusability of the SOC verification system.

关 键 词：SOC验证 FPGA系统 JTAG定制 

分 类 号：TN47[电子电信—微电子学与固体电子学]