RS(255,247)译码器的FPGA实现  

Implementation of FPGA for RS(255,247) Decoder

作　　者：张泽云[1] 徐朝阳[2] 张友益[2] 

机构地区：[1]江苏科技大学,镇江212003 [2]船舶重工集团公司723所,扬州225001

出　　处：《舰船电子对抗》2009年第1期92-95,120,共5页Shipboard Electronic Countermeasure

摘　　要：RS码是差错控制领域中一类重要的线性分组码,由于其出众的纠错能力,因而被广泛地应用于各种差错控制系统中,以满足对数据传输通道可靠性的要求。利用现场可编程门阵列(FPGA)技术由VHDL语言来实现RS(255,247)译码方案并应用于一种大容量的存储设备以提高数据传输和存储的可靠性。对所设计的硬件系统在ISE10.1平台上用VHDL进行了行为仿真和时序仿真,并给出了仿真波形图。The reed solomon （RS） code is a kind of important linear block code in error control field. As a result of its superior correction ability,the RS code has been widely used in various error control systems to satisfy the request for reliability of data transmission channel. This paper uses the field-programmable gate array （FPGA） technique to implement RS（255,247） decoding project based on VHDL,and applies it to a large capacity memory equipment to improve the reliability of data transmission and memory,implements the behavioral simulation and time sequence simulation for the designed hardware system based on the ISE10. 1 platform with VHDL, and gives out the simulative oscillogram.

关 键 词：RS译码器 BERLEKAMP-MASSEY算法 现场可编程门阵列 数据传输 

分 类 号：TN911.22[电子电信—通信与信息系统]