高阶∑△ADC的抽取滤波器的设计  

Design of a Decimation Filter Used in ∑△ADC

作　　者：曾健平[1] 孙凡博[1] 叶英[1] 谢海情[1] 章兢[1] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《湖南大学学报（自然科学版）》2009年第3期36-39,共4页Journal of Hunan University:Natural Sciences

基　　金：湖南省科技计划资助项目(2008FJ3123);湖南省研究生科研创新资助项目

摘　　要：通过优化和改进梳状滤波器结构,采用FIR补偿滤波器以补偿通带衰减,并合理安排硬件电路以节省面积,设计了一种高速、低功耗高阶∑△ADC中的抽取滤波器.应用Matlab进行电路仿真,该滤波器阻带衰减为-65 dB,通带纹波为±0.05 dB,过渡带为0.454fs^0.583fs.经过VerilogXL和系统验证,该滤波器完全满足∑△ADC的系统要求.The decimation filter used in high-order ∑△ADC（Analog Digital Converter） was given. Considering the hardware implement and minimizing the power dissipation, some techniques were applied to optimize the Cascade Integrator Comb（CIC） filter structure. The Finite Impulse Response（FIR） droop correction filter was also presented to correct the pass band droop of CIC filter. The speed of this filter was improved and the area was minimized by using the correct circuit structure. The results from Matlab simulation have shown that the filter has stopped band attenuation of - 65 dB, pass band ripple of ± 0.05 dB and the transition band of 0. 454fs --0. 583fs. According to the simulation of VerilogXL and the system, the filter well meets the demands of high-order ∑△ADC.

关 键 词：滤波器 ADC 有限冲激响应 进位保留加法器 

分 类 号：TN911.7[电子电信—通信与信息系统]