基于FPGA的脑机接口实时系统  

Real-time system of brain-computer interface based on FPGA

作　　者：王永[1] 何庆华[2] 田逢春[1] 徐江[1] 冯正权[2] 

机构地区：[1]重庆大学通信工程学院,重庆400044 [2]第三军医大学大坪医院野战外科研究所创伤,烧伤与复合伤国家重点实验室,重庆400042

出　　处：《电子技术应用》2009年第4期133-136,共4页Application of Electronic Technique

基　　金：国家自然科学基金项目资助(编号:30300418);重庆市自然科学基金资助项目(编号:CSTC;2005BB2187)

摘　　要：给出了以FPGA为核心,实现基于瞬态视觉诱发电位的脑机接口实时系统的方案。该方案包括脑电采集电路、基于FPGA的VGA视觉刺激器和FPGA开发板三部分。用FPGA取代计算机,作为脑机接口的控制和信息处理器。利用VHDL编程,在FPGA中实时处理采集的脑电信号,提取并识别瞬态视觉诱发电位信号,转换为控制命令,反馈给视觉刺激器。实验结果表明,本方案可以有效地实现脑机接口实时系统,并达到较高的正确率和通信速度。The paper describes a scheme focused on FPGA, realize real-time brain-computer interface based on transient visual evoked potential. The scheme includes three parts： EEG collection circuit, VGA visual stimulator based on FPGA and FPGA development board. Instead of computer, FPGA is used as controller and data processor of brain-computer interface. The programming language VHDL is used to implement real-time processing of EEG, extraction and recognition of transient visual evoked potential, to generate control command and feed back to visual stimulator in FPGA. Experimental results indicate that the scheme may be valuable for developing real brain-computer interface with relatively high accuracy and speed.

关 键 词：脑机接口 FPGA 视觉诱发电位 视觉刺激器 提取和识别 

分 类 号：TN911.7[电子电信—通信与信息系统]