分步式并行MQ编码及其VLSI设计  

A separate parallel MQ coder and its VLSI architecture

作　　者：王前[1] 吕东强[2] 

机构地区：[1]北京航空航天大学计算机学院数字媒体实验室,北京100083 [2]第二炮兵装备研究院四所,北京100085

出　　处：《高技术通讯》2009年第3期247-252,共6页Chinese High Technology Letters

基　　金：863计划(2006AA701121);教育部博士点基金和新世纪优秀人才支持计划资助项目

摘　　要：针对MQ编码的环路反馈结构的高复杂度对实现快速图像压缩硬件的限制,研究分析了MQ编码的基本算法,提出了'区间编码'和'位填充'之间有一定的独立性,可用先进先出(FIFO)管道连接后并行处理的思想,并设计了一种适合MQ编码算法特点的异步流水线与有限状态机(FSM)相结合的分步式并行结构。该结构简单合理,FIFO管道的引入可支持异步流水电路,FSM的动态优化策略有效地防止了流水的阻塞,复杂环路的逐层分解显著降低了编码的反馈效应,根据程序运行过程中的数据操作动态特征,利用概率统计规律和状态机分割减小了系统的关键路径长度。该结构的资源利用率高,现场可编程门阵列(FPGA)原型系统最高时钟工作频率为233MHz,吞吐率与其它同类结构相比有明显提高,达到116.5Mbps。In view of the fact that the MQ encoder＇s high complex loop feedback structure restricts its fast image compression hardware implementation, the paper proposes the concept that the encoding module and the bit stuffing module can be connected by FIFO channel and operated simultaneously for their independency based on the analysis of the original MQ coding algorithm, and gives the design of a separate parallel architecture combining asynchronous pipelining with the finite state machine （FSM）, which is suitable for software algorithm characteristics. Based on the dynamic feature of data operation in the processing of program, the length of the critical path is reduced by the probability statistical law and the division technology of the state machine. The experimental results show that the architecture is with a high resource uti- lization ratio, and its throughput rate is significantly increased to 116.5Mbps at the highest working frequency of 233MHz on a field-programmable gate array （FPGA） prototype chip compared with the up-to-date design.

关 键 词：算术编码 分步式 图像压缩 关键路径 

分 类 号：TN762[电子电信—电路与系统]