一种适用于流水线ADC的数字校准算法的硬件实现  

The hardware realization of a digital background calibration technique for pipelined A/D converters

作　　者：郭静宜[1] 李冬梅[1] 刘力源[2] 李福乐[2] 

机构地区：[1]清华大学电子工程系,北京100084 [2]清华大学微电子研究所,北京100084

出　　处：《高技术通讯》2009年第3期290-294,共5页Chinese High Technology Letters

基　　金：国家自然科学基金(60475018)资助项目

摘　　要：研究了一种适用于开关电容级电路结构的流水线ADC的数字后台校准算法并提出了其硬件实现方法。此算法适用于每级1.5bit和多bit的子级转换电路,实时地监控关键子级电路转换函数的特性,并从数字输出中提取校准信息,不中断正常的转换过程。文中提出的硬件实现方法通过有限状态机实现该算法,实现了各模块高效的协同工作。仿真证明用该硬件实现方法设计的校准处理系统能够有效校准电容失配和运放有限增益误差。This paper researches a digital background calibration technique for switched-capacitor CMOS pipelined analog-todigital converters （ADC） and describes its hardware implementation. It is applicable in both 1.5-bit and multi-bit pipeline stages. It can monitor the crucial substage＇ s transfer characteristics and extracts the calibration information from the digital domain without interrupting the normal conversion process. The hardware realization is implemented by the finite state machine so the effective work between different modules can be implemented. It is proved by simulation that the hardware implementation can calibrate the capacitor mismatches and finite OPAMP＇s gain error.

关 键 词：流水线ADC 数字校准 后台 

分 类 号：TN792[电子电信—电路与系统] TM933.4[电气工程—电力电子与电力传动]