一种基于单电子晶体管的全加器电路设计  

A Full Adder Design using Single Electron Transistors

作　　者：吴刚[1] 蔡理[1] 王森[1] 李芹[1] 

机构地区：[1]空军工程大学理学院,陕西西安710051

出　　处：《微计算机信息》2009年第11期298-300,共3页Control & Automation

摘　　要：基于单电子晶体管的I-V特性和传输晶体管的设计思想,用多栅单电子晶体管作为传输晶体管,设计了一个由5个SET构成的全加器,相对于静态互补逻辑设计的全加器,本文设计的全加器在器件数量上大大减少,有利于大规模电路的设计。仿真结果表明,本文设计的全加器电路具有高速与低功耗的特性。Based on the I-V characteristics of single electron transistor （SET） and the concept of the single electron pass-transistor, a sort of full adder composed of 5 SET is proposed using the multi-gate single-electron transistor as pass-transistor. Comparing with the full adder based on the method of static complementary logic, the amount of device is reduced largely. The result of simulation indi（ated that the full adder exhibit s smaller signal delay and lower power dissipation.

关 键 词：单电子晶体管 传输晶体管:全加器 

分 类 号：TN321[电子电信—物理电子学]