Turbo乘积码技术及其FPGA实现  

Turbo Product Codes and Its Realization in FPGA

作　　者：王晓波[1] 罗霞[2] 孙甲琦[1] 

机构地区：[1]航天科技集团公司第七○四研究所,北京100076 [2]西北工业大学,西安710072

出　　处：《遥测遥控》2007年第2期31-36,共6页Journal of Telemetry,Tracking and Command

摘　　要：介绍Turbo乘积码的基本概念,对chase译码算法、硬判决码字的可靠性计算、串行和并行迭代译码算法及其FPGA硬件描述语言的实现作了介绍和仿真,给出了仿真的译码性能曲线。The basic principles of turbo product codes are introduced in this paper.Then the chase algorithm,the reliability computa- tion of hard-decision code word,the serial iterative decoding algorithm and the parallel iterative decoding algorithm are described.Finally the decoding performance curves from the simulation of the algorithms described above in FPGA are given.

关 键 词：TURBO乘积码 chase译码 硬判决码字 迭代译码 

分 类 号：TN911.22[电子电信—通信与信息系统] TN791[电子电信—信息与通信工程]