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机构地区:[1]Microelectronics Center Southeast University, Nanjing 210018 [2]The Planning Committee of Hefei City, Hefei 230061
出 处:《Journal of Electronics(China)》1994年第2期104-115,共12页电子科学学刊(英文版)
基 金:Supported by the National Native Science Foundation of China
摘 要:This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.
关 键 词:CMOS DIGITAL integrated CIRCUITS TRANSIENT characteristics High TEMPERATURE CMOS
分 类 号:TN432[电子电信—微电子学与固体电子学]
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