基于PC并口的定时信号发生器的设计实践  

Design Practice of Timing Signal Generator Based on PC Parallel Port

作　　者：李震涛[1] 

机构地区：[1]中北大学,山西省太原市030000

出　　处：《信息化研究》2009年第3期23-25,36,共4页INFORMATIZATION RESEARCH

摘　　要：现代雷达尤其是MTI(动目标显示)、MTD(动目标检测)以及脉冲多普勒雷达对发射机的稳定性要求越来越高,因此对发射机内的定时信号的要求也越来越高,采用高频率稳定度晶振及全数字电路组成的定时信号发生器能满足发射机的要求。文中介绍了一种采用PC并口EPP(增强型并行端口)模式控制的以EPLD(电可编程逻辑器件)为核心的定时信号发生器组成框图及信号产生的原理,并给出了仿真结果。The requirement to qualify of timing signal in the transmitter becomes more and more exacting as the requirement to the stability of the modern radar, especially MTI, MTD and pulse dopple radar is becoming higher and higher. The timing signal generator using crystal oscillator with high stability and composed of all digital circuit can meet the requirements of the transmitter. A timing signal generator employing PC parallel port EPP mode with EPLD as its core is introduced in this paper. The composition block diagram is presented, and the signal generating principle is discussed. The simulation results are presented, too.

关 键 词：定时信号发生器 并口 EPLD 发射机 

分 类 号：TN957.3[电子电信—信号与信息处理]