单精度浮点加法器的FPGA实现  

Implementation of Single Precision Floating Point Adder Based on FPGA

作　　者：王顺[1] 戴瑜兴[1] 

机构地区：[1]湖南大学电气与信息工程学院,湖南长沙410082

出　　处：《现代电子技术》2009年第8期8-10,共3页Modern Electronics Technique

摘　　要：在FPGA上实现单精度浮点加法器的设计,通过分析实数的IEEE 754表示形式和IEEE 754单精度浮点的存储格式,设计出一种适合在FPGA上实现单精度浮点加法运算的算法处理流程,依据此算法处理流程划分的各个处理模块便于流水设计的实现。所以这里所介绍的单精度浮点加法器具有很强的运算处理能力。A design of single precision floating point adder based on FPGA is presented, by analysing the form of real number formed on IEEE 754 and the storage format of IEEE 754 single precision floating point, the addition arithmetic process which is easy to realized by using FPGA is put forward, the split of module based on the arithmetic process facilitates the realization of pipeline designing, so the single precision floating point adder has powerful operation process ability.

关 键 词：IEEE 754 单精度浮点 加法运算 FPGA 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]