高速网络安全协处理器中PCI-X接口设计  

Design of PCI-X Interface for High Speed Network Security Co-processor

作　　者：朱莹[1] 白国强[1] 陈弘毅[1] 

机构地区：[1]清华大学微电子学研究所信息科学与技术国家实验室,北京100084

出　　处：《计算机工程》2009年第7期212-214,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(60576027;60544008);国家"863"计划基金资助项目(2006AA01Z415)

摘　　要：介绍高速网络安全协处理器中PCI-X接口模块的设计方法,利用IPSec和SSL/TLS2种协议优化系统,并配置各种算法引擎。协处理器采用具有更高性能的PCI-X总线接口及SoC芯片,能够同时满足PCI-X总线协议和协处理器内部的特殊传输要求。实验结果表明,该设计方法是可行的。The method to design PCI-X interface for high speed network security co-processor is introduced, which uses two protocols such as IPSec and SSL/TLS protocols to optimize the system, and deploys different kinds of algorithm engines. The co-processor uses PCI-X bus interface and SoC chip with higher performance, which meets the requirement of both PCI-X bus protocol and the internal data transfers of co-processor. Experimental results show this method is feasible.

关 键 词：PCI-X总线接口 密码安全 协处理器 

分 类 号：TP311.5[自动化与计算机技术—计算机软件与理论]