可编程逻辑器件设计中的亚稳态问题及解决方案  

The Metastability and Solutions Method in CPLD Design

作　　者：李立[1] 龙泳涛[1] 曾钢燕[1] 程春红[1] 陈意军[1] 

机构地区：[1]湖南工程学院电气与信息工程学院,湖南湘潭411101

出　　处：《湘潭大学自然科学学报》2009年第1期125-129,共5页Natural Science Journal of Xiangtan University

基　　金：湖南省自然科学基金(05JJ40094)

摘　　要：分析了可编程逻辑器件设计中亚稳态产生的原因及亚稳态评估方法,介绍了几种解决亚稳态问题的常用策略.针对这些常用方法不能彻底消除亚稳态的不足,提出了一种基于使能触发器构成的"高频时钟错位法",这种方法通过从外部引入一个高频脉冲,对原来互相独立的异步时钟信号同步在高频时钟的上升沿和下降沿,并且保持半周期的时间间隔.只要选择适当的高频时钟频率和电路参数,亚稳态可以得到完全消除.这种方法在数字系统设计中有广阔的应用前景.The causes and assessment methods of metastability in CPLD（Complex Programmable Logic Deviee）are analyzed. The several common design strategy to solve the problems of metastability are introduced. Due to the deficiency of these methods,a Logic controller named ＂High-frequency clock spacing Synchronizer ＂ is designed by taking advantage by means of Enable D triggerand and a high-frequency pulse from the outside introduction. Asynchronous clocks are synchroned to the rising edge and falling edge respectively of high-frequent eloek. Thus quite dose Independent clocks are separraled to a time interval of half period. In Conclusion, so long as select appropriately time of delay and High-frequency clock, the occurrence of metastability in circuit could be totally avoided. This method has wide application prospects for digital system design.

关 键 词：可编程逻辑器件 异步 亚稳态 高频时钟错位法 

分 类 号：TN4[电子电信—微电子学与固体电子学]